<em>Computer-Aided Verification</em> is a collection of papers that begins with a general survey of hardware verification methods. Ms. Gupta starts with the issue of verification itself and develops a
taxonomy of verification methodologies, focusing especially upon recent advances. Although her emphasis is hardware verification, most of what she reports applies to software verification as well. <br/> Graphical
presentation is coming to be a <em>de facto</em> requirement for a `friendly' user interface. The second paper presents a generic format for graphical presentations of coordinating systems represented by
automata. <br/> The last two papers as a pair, present a variety of generic techniques for reducing the computational cost of computer-aided verification based upon explicit computational memory: the first of the two
gives a time-space trade-off, while the second gives a technique which trades space for a (sometimes predictable) probability of error. <br/> <em>Computer-Aided Verification</em> is an edited volume of
original research. This research work has also been published as a special issue of the journal <em>Formal Methods in System Design, 1:2-3</em>. <br/>