<em>Logic Synthesis for Low Power VLSI Designs</em> presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed
presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. <em>Logic Synthesis for Low Power VLSI Designs</em> contains
detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the
trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation
goal while meeting the timing constraints. <br/> <em>Logic Synthesis for Low Power VLSI Designs</em> is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of
CMOS digital design and logic synthesis.